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| MX25UM51245G MX25UM51245G rev. 0.00, nov. 24, 2014 advanced information
2 contents 1. features .............................................................................................................................................................. 4 2. general description ..................................................................................................................................... 6 table 1. operating frequency comparison ....................... ......................................................................... 6 3. pin configurations ......................................................................................................................................... 7 4. pin description .................................................................................................................................................. 7 5. block diagram ................................................................................................................................................... 8 6. data protection ................................................................................................................................................ 9 7. memory organization ........................................................................................................................................... 10 table 2. memory organization .................................................................................................................. 10 table 3. protected area sizes ....................... ............................................................................................ 11 table 4. 4k-bit secured otp defnition ....................... ............................................................................. 12 8. deice operation ............................................................................................................................................ 13 9. command description ................................................................................................................................... 15 table 5. spi command set ....................... ................................................................................................ 15 table 6. opi command set ....................... ............................................................................................... 18 9-1. status register ... ..................................................................................................................................... 22 9-2. confguration register ............................................................................................................................. 23 9-3. confguration register 2 .......................................................................................................................... 24 9-4. security register .. ................................................................................................................................... 25 table 7. security register defnition ......................................................................................................... 25 9-5. w rite enable (wren) ... ........................................................................................................................... 26 9-6. w rite disable (wrdi) ............................................................................................................................... 27 9-7. read identifcation (rdid) ... .................................................................................................................... 28 table 8. id defnitions .............................................................................................................................. 28 9-8. read status register (rdsr) ................................................................................................................. 29 9-9. read confguration register (rdcr) ... ................................................................................................... 32 9-10. w rite status register (wrsr) / write confguration register (wrcr) .................................................. 33 9-11. read confguration register 2 (rdcr2) ... .............................................................................................. 36 9-12. write confguration register 2 (wrcr2) ................................................................................................. 37 9-13. read security register (rdscur) ......................................................................................................... 38 9-14. w rite security register (wrscur) ......................................................................................................... 39 9-15. read data bytes (read) ... ..................................................................................................................... 40 9-16. read data bytes at higher speed (f ast_read) ... ............................................................................... 41 9-17. oct a read mode (8read) .................................................................................................................... 42 9-18. oct a dtr read mode (8dtrd) ... ......................................................................................................... 43 9-19. preamble bit ............................................................................................................................................ 44 9-20. burst read ... ............................................................................................................................................ 45 9-21. fast boot .. ............................................................................................................................................... 46 9-22. sector erase (se) .................................................................................................................................... 51 9-23. block erase (be) ..................................................................................................................................... 52 9-24. chip erase (ce) ....................................................................................................................................... 53 9-25. page program (pp) ................................................................................................................................. 54 MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 3 9-26. deep power-down (dp) ........................................................................................................................... 56 9-27. release from deep power-down (rdp) .................................................................................................. 57 9-28. enter secured otp (enso) .................................................................................................................... 58 9-29. exit secured otp (exso) ... .................................................................................................................... 58 9-30. individual sector protection ..................................................................................................................... 59 9-31. program/erase suspend/resume ........................................................................................................... 66 9-32. erase suspend ........................................................................................................................................ 66 9-33. program suspend .................................................................................................................................... 66 9-34. write-resume ... ....................................................................................................................................... 68 9-35. no operation (nop) ................................................................................................................................ 68 9-36. software reset (reset-enable (rsten) and reset (rst)) ................................................................... 68 9-37. read sfdp mode (rdsfdp) .................................................................................................................. 70 table 9. signature and parameter identifcation data values (tbd) ........................................................ 71 10. reset.................................................................................................................................................................. 72 table 10. reset timing-(power on) ....................... ................................................................................... 72 table 11. reset timing-(other operation) ................................................................................................ 72 11. power-on state ............................................................................................................................................. 73 12. electrical specifications ........................................................................................................................ 74 table 12. absolute maximum ratings ............................................................................................ 74 table 13. capacitance ta = 25c, f = 1.0 mhz .................................................................................... 74 table 14. dc characteristics .......................................................................................................... 76 table 15. ac characteristics ....................... .................................................................................... 77 13. operating conditions ................................................................................................................................. 79 table 16. power-up/down voltage and timing ....................... ................................................................. 81 13-1. initial delivery state ...................................................................................................................... 81 14. erase and programming performance .............................................................................................. 82 15. data retention .............................................................................................................................................. 82 16. latch-up characteristics ........................................................................................................................ 82 17. ordering informa tion ................................................................................................................................ 83 18. part name description ............................................................................................................................... 84 19. package information .................................................................................................................................. 85 MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 4 1. features general ? supports serial peripheral interface -- mode 0 ? single power supply operation - 1.7 to 2.0 volt for read, erase, and program operations ? 512mb: 536,870,912 x 1 bit structure or 67,108,846 x 8 bits (octa i/o mode) structure ? protocol support - single i/o and octa i/o ? latch-up protected to 100ma from -1v to vcc +1v ? low vcc write inhibit is from 1.0v to 1.4v ? fast frequency support - support clock frequency up to - single i/o mode: 133mhz - octa i/o mode: 200mhz - confgurable dummy cycle number for opi read operation ? octa peripheral interface (opi) available ? equal sectors with 4k byte each, or equal blocks with 64k byte each - any block can be erased individually ? programming : - 256byte page buf fer - octa input/output page program to enhance program performance ? t ypical 100,000 erase/program cycles ? 20 years data retention softw are features ? input data format - 2-byte command code ? advanced security features - block lock protection the bp0-bp3 and t/b status bits defne the size of the area to be protected against program and erase instructions - individual sector protection (solid protect) ? additional 4k bit security otp - features unique identifer - factory locked identifable, and customer lockable ? command reset ? program/erase suspend and resume operation ? electronic identifcation - jedec 1-byte manufacturer id and 2-byte device id ? support serial flash discoverable parameters (sfdp) mode 1.8v 512m-bit [x 1/x 8] cmos mxsmio ? (serial multi i/o) flash memory MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 5 hardware features ? sclk input - serial clock input ? sio0 - sio7 - serial data input or serial data output ? dqs - data strobe signal ? reset# - hardware reset pin ? p ackage -24-ball bga (5x5 ball array) -all devices are rohs compliant and halogen free. MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 6 2. general description MX25UM51245G is 512mb bits serial flash memory, which is configured as 67,108,864 x 8 internally. MX25UM51245G feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single i/o mode. the three bus signals are a clock input (sclk), a serial data input (si), and a serial data output (so). serial access to the device is enabled by cs# input. the MX25UM51245G mxsmio ? (serial multi i/o) provides sequential read operation on whole chip. after program/erase command is issued, auto program/erase algorithms which program/erase and verify the specifed page or sector/block locations will be executed. progr am command is executed on byte basis, or page (256 bytes) basis, or word basis for erase command is executed on sector (4k-byte), or block (64k-byte), or whole chip basis. to provide user with ease of interface, a status register is included to indicate the status of the chip. the status read command can be issued to detect completion status of a program or erase operation via wip bit. when the device is not in operation and cs# is high, it is put in standby mode. the MX25UM51245G utilizes macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. table 1. operating frequency comparison numbers of dummy cycle 6 8 10 12 14 16 18 20 octa i/o str (mhz) 66 84 104 104 133 166 166 200* octa i/o dtr (mhz) 66 84 104 104 133 166 166 200* notes: * means default status MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 7 3. pin configurations 4. pin description symbol description cs# chip select si/sio0 serial data input (for 1 x i/o)/ serial data input & output (for 8xi/o read mode) so/sio1 serial data output (for 1 x i/o)/ serial data input & output (for 8xi/o read mode) sclk clock input sio2-sio7 serial data input & output (for 8xi/o read mode) reset# hardware reset pin active low note 1 vcc + 1.8v power supply vccq io buffer power supply gnd ground vssq io ground supply dqs data strobe signal nc no connection notes: 1. reset# pin has internal pull up. 24-ball bga (5x5 ball array) reset# vcc sio2 sio3 vccq nc gnd vssq sio0 sio5 nc sclk sio1 sio6 nc nc nc dqs sio4 vssq nc vccq sio7 cs# a b c d e 1 2 3 4 5 MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 8 5. block diagram address generator memory array page buffer y-decoder x-decoder data register sram buffer si/sio0 sclk so/sio1 sio2-sio7 dqs clock generator state machine mode logic sense amplifier hv generator output buffer cs# reset# MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 9 6. data protection during power transition, there may be some false system level signals which result in inadvertent erasure or programming. the device is designed to protect itself from these accidental write cycles. the state machine will be reset as standby mode automatically during power up. in addition, the control register architecture of the device constrains that the memory contents can only be changed after specifc command sequences have completed successfully. in the following, there are several features to protect the system from the accidental write cycles during vcc power- up and power-down or from system noise. ? v alid command length (spi mode) or command/command# combination (opi mode) will be check. ? w rite enable (wren) command: wren command is required to set the write enable latch bit (wel) before other command to change data. ? deep power down mode: by entering deep power down mode, the fash device also is under protected from writing all commands except release from deep power down mode command (rdp) and read electronic signature command (res), and softreset command. MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 10 table 2. memory organization 7. memory organization sector 16383 3fff000h 3ffffffh ? 16376 3ff8000h 3ff8fffh 16375 3ff7000h 3ff7fffh ? 16368 3ff0000h 3ff0fffh 16367 3fef000h 3feffffh ? 16360 3fe8000h 3fe8fffh 16359 3fe7000h 3fe7fffh ? 16352 3fe0000h 3fe0fffh 16351 3fdf000h 3fdffffh ? 16344 3fd8000h 3fd8fffh 16343 3fd7000h 3fd7fffh ? ? ? ? ? ? ? ? ? ? ? ? ? 16336 3fd0000h 3fd0fffh 47 002f000h 002ffffh ? 40 0028000h 0028fffh 39 027000h 0027fffh ? 32 0020000h 0020fffh 31 001f000h 001ffffh ? 24 0018000h 0018fffh 23 0017000h 0017fffh ? 16 0010000h 0010fffh 15 000f000h 000ffffh ? 8 0008000h 0008fffh 7 0007000h 0007fffh ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0000000h 0000fffh address range block(64k-byte) 1021 2 1 0 1023 1022 MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 11 table 3. protected area sizes status bit protect level bp3 bp2 bp1 bp0 512mb 0 0 0 0 0 (none) 0 0 0 1 1 (1 block, protected block 1023rd) 0 0 1 0 2 (2 blocks, protected block 1022nd~1023rd) 0 0 1 1 3 (4 blocks, protected block 1020th~1023rd) 0 1 0 0 4 (8 blocks, protected block 1016th~1023rd) 0 1 0 1 5 (16 blocks, protected block 1008th~1023rd) 0 1 1 0 6 (32 blocks, protected block 992nd~1023rd) 0 1 1 1 7 (64 blocks, protected block 960th~1023rd) 1 0 0 0 8 (128 blocks, protected block 896th~1023rd) 1 0 0 1 9 (256 blocks, protected block 768th~1023rd) 1 0 1 0 10 (512 blocks, protected block 512nd~1023rd) 1 0 1 1 11 (1024 blocks, protected all) 1 1 0 0 12 (1024 blocks, protected all) 1 1 0 1 13 (1024 blocks, protected all) 1 1 1 0 14 (1024 blocks, protected all) 1 1 1 1 15 (1024 blocks, protected all) status bit protect level bp3 bp2 bp1 bp0 512mb 0 0 0 0 0 (none) 0 0 0 1 1 (1 block, protected block 0th) 0 0 1 0 2 (2 blocks, protected block 0th~1th) 0 0 1 1 3 (4 blocks, protected block 0th~3rd) 0 1 0 0 4 (8 blocks, protected block 0th~7th) 0 1 0 1 5 (16 blocks, protected block 0th~15th) 0 1 1 0 6 (32 blocks, protected block 0th~31st) 0 1 1 1 7 (64 blocks, protected block 0th~63rd) 1 0 0 0 8 (128 blocks, protected block 0th~127th) 1 0 0 1 9 (256 blocks, protected block 0th~255th) 1 0 1 0 10 (512 blocks, protected block 0th~511st) 1 0 1 1 11 (1024 blocks, protected all) 1 1 0 0 12 (1024 blocks, protected all) 1 1 0 1 13 (1024 blocks, protected all) 1 1 1 0 14 (1024 blocks, protected all) 1 1 1 1 15 (1024 blocks, protected all) protected area sizes (t/b bit = 1) protected area sizes (t/b bit = 0) i. block lock protection - the software protected mode (spm) use (bp3, bp2, bp1, bp0 and t/b) bits to allow part of memory to be protected as read only. the protected area defnition is shown as table 3 protected area sizes, the protected areas are more fexible which may protect various area by setting value of bp0-bp3 bits. MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 12 ii. additional 4k-bit secured otp for unique identifer: to provide 4k-bit one-time program area for setting device unique serial number - which may be set by factory or system customer. - security register bit 0 ind icates whether the chip is locked by factory or not. - to program the 4k-bit secured otp by entering 4k-bit secured otp mode (with enter security otp command), and going through normal program procedure, and then exiting 4k-bit secured otp mode by writing exit security otp command. - customer may lock-dow n the customer lockable secured otp by writing wrscur(write security register) command to set customer lock-down bit1 as "1". please refer to "table 7. security register defnition" for security register bit defnition and "table 4. 4k-bit secured otp defnition" for address range defnition. - note: once lock-down whatever by factory or customer , it cannot be changed any more. while in 4k-bit secured otp mode, array access is not allowed. table 4. .elw6hfxuhg273hqlwlrq address range size standard factory lock customer lock xxx000~xxx00f 128-bit esn (electrical serial number) determined by customer xxx010~xxx1ff 3968-bit n/a MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 13 8. device operation 1. before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2. when incorrect command# sequence is inputted to this device, this device becomes standby mode and keeps the standby mode until next cs# falling edge. in standby mode, so pin of this device should be high-z. 3. when correct command# sequence is inputted to this device, this device becomes active mode and keeps the active mode until next cs# rising edge. 4. when device under str mode, input data is latched on the rising edge of serial clock (sclk) and data shifts out on the falling edge of sclk. when device under dtr mode, input data is latched on the both rising and falling edge of serial clock (sclk) and data shifts out on both rising and falling edge of sclk. 5. while a w rite status register, program or erase operation is in progress, access to the memory array is neglected and not affect the current operation of write status register, program, erase. figure 1. input timing (str mode) sclk sio cs# msb tdvch lsb tslch tchdx tchcl tclch tshch tshsl tchsh tchsl figure 2. input timing (dtr mode) sclk tdvch tslch tchcl tshch tclsh tchsl cs# tshsl sio msb lsb tchdx tcldx tdvcl tclch MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 14 figure 3. output timing (str mode) lsb tshqz tch tcl tclqx tclqv tclqx tclqv sclk sio cs# figure 4. output timing (dtr mode) sclk dqs tchqv tqxqs tclqv sio[7:0] tqsqv tqsqv tqxqs MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 15 9. command description table 5. spi command set read/write array commands command (byte) read (normal read) fast read (fast read data) rdid (read identifcation) rdsfdp 1st byte 13 (hex) 0c (hex) 9f (hex) 5a (hex) 2nd byte add1 add1 add1 3rd byte add2 add2 add2 4th byte add3 add3 add3 5th byte add4 add4 6th byte dummy(8) data cycles action n bytes read out until cs# goes high n bytes read out until cs# goes high outputs jedec id: 1-byte manufacturer id & 2-byte device id read sfdp mode command (byte) pp (page program) se (sector erase) be (block erase 64kb) ce (chip erase) 1st byte 12 (hex) 21 (hex) dc (hex) 60 or c7 (hex) 2nd byte add1 add1 add1 3rd byte add2 add2 add2 4th byte add3 add3 add3 5th byte add4 add4 add4 6th byte data cycles 1-256 action to program the selected page to erase the selected sector to erase the selected block to erase whole chip MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 16 setting commands command (byte) wren (write enable) wrdi (write disable) pgm/ers suspend (suspends program/ erase) pgm/ers resume (resumes program/ erase) dp (deep power down) 1st byte 06 (hex) 04 (hex) b0 (hex) 30 (hex) b9 (hex) 2nd byte 3rd byte 4th byte 5th byte data cycles action sets the (wel) write enable latch bit resets the (wel) write enable latch bit enters deep power down mode command (byte) rdp (release from deep power down) sbl (set burst length) enso (enter secured otp) exso (exit secured otp) 1st byte ab (hex) c0 (hex) b1 (hex) c1 (hex) 2nd byte 3rd byte 4th byte 5th byte data cycles 1 action release from deep power down mode to set burst length to enter the 4k-bit secured otp mode to exit the 4k-bit secured otp mode reset commands command (byte) nop (no operation) rsten (reset enable) rst (reset memory) 1st byte 00 (hex) 66 (hex) (note 2) 99 (hex) (note 2) 2nd byte 3rd byte 4th byte 5th byte action MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 17 note 1: it is not recommended to adopt any other code/address not in the command defnition table, which will potentially enter the hidden mode. note 2: before executing rst command, rsten command must be executed. if there is any other command to interfere, the reset operation will be disabled. note 3: the number in parentheses after "add" or "data" stands for how many clock cycles it has. for example, "data(8)" repre - sents there are 8 clock cycles for the data in. command (byte) wrfbr (write fast boot register) esfbr (erase fast boot register) rdscur (read security register) wrscur (write security register) wrlr (write lock register) rdlr (read lock register) 1st byte 17 (hex) 18 (hex) 2b (hex) 2f (hex) 2c (hex) 2d (hex) 2nd byte 3rd byte 4th byte 5th byte data cycles 4 2 2 action to read value of security register to set the lock- down bit as "1" (once lock- down, cannot be updated) register commands command (byte) rdsr (read status register) rdcr (read confguration register) wrsr (write status/ confguration register) rdcr 2 (read confguration register 2) wrcr2 (write confguration register 2 ) rdfbr (read fast boot register) 1st byte 05 (hex) 15 (hex) 01 (hex) 71 (hex) 72 (hex) 16 (hex) 2nd byte add1 add1 3rd byte add2 add2 4th byte add3 add3 5th byte add4 add4 data cycles 1 1 1-2 1 1 1-4 action to read out the values of the status register to read out the values of the confguration register to write new values of the status/ confguration register command (byte) wrspb (spb bit program) esspb (all spb bit erase) rdspb (read spb status) mode spi spi spi address bytes 4 0 4 1st byte e3 (hex) e4 (hex) e2 (hex) 2nd byte add1 add1 3rd byte add2 add2 4th byte add3 add3 5th byte add4 add4 data cycles 1 action MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 18 table 6. opi command set read/write array commands command (byte) 8read (octa io read) 8dtrd (octa io dt read) rdid (read identifcation) rdsfdp 1st byte ec (hex) ee (hex) 9f (hex) 5a (hex) 2nd byte 13 (hex) 11 (hex) 60 (hex) a5 (hex) 3rd byte add1 add1 00h add1 4th byte add2 add2 00h add2 5th byte add3 add3 00h add3 6th byte add4 add4 (note 6) 00h add4 7th byte dummy (note 4) dummy (note 4) dummy(20) data cycles 3 (note 8) action octa i/o str read octa i/o dtr read outputs jedec id: 1-byte manufacturer id & 2-byte device id read sfdp mode command (byte) pp (page program) se (sector erase) be (block erase 64kb) ce (chip erase) 1st byte 12 (hex) 21 (hex) dc (hex) 60 or c7 (hex) 2nd byte ed (hex) de (hex) 23 (hex) 9f or 38 (hex) 3rd byte add1 add1 add1 4th byte add2 add2 add2 5th byte add3 add3 add3 6th byte add4 (note 6) add4 add4 7th byte data cycles 1-256 action to program the selected page to erase the selected sector to erase the selected block to erase whole chip MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 19 setting commands command (byte) wren (write enable) wrdi (write disable) pgm/ers suspend (suspends program/ erase) pgm/ers resume (resumes program/ erase) dp (deep power down) 1st byte 06 (hex) 04 (hex) b0 (hex) 30 (hex) b9 (hex) 2nd byte f9 (hex) fb (hex) 4f (hex) cf (hex) 46 (hex) 3rd byte 4th byte 5th byte 6th byte 7th byte data cycles sets the (wel) write enable latch bit resets the (wel) write enable latch bit enters deep power down mode command (byte) rdp (release from deep power down) sbl (set burst length) enso (enter secured otp) exso (exit secured otp) 1st byte ab (hex) c0 (hex) b1 (hex) c1 (hex) 2nd byte 54 (hex) 3f (hex) 4e (hex) 3e (hex) 3rd byte 00h 4th byte 00h 5th byte 00h 6th byte 00h 7th byte 1 data cycles release from deep power down mode to set burst length to enter the 4k-bit secured otp mode to exit the 4k-bit secured otp mode reset commands command (byte) nop (no operation) rsten (reset enable) rst (reset memory) 1st byte 00 (hex) 66 (hex) (note 2) 99 (hex) (note 2) 2nd byte ff (hex) 99 (hex) 66 (hex) 3rd byte 4th byte 5th byte 6th byte data cycles MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 20 command (byte) rdfbr (read fast boot register) wrfbr (write fast boot register) esfbr (erase fast boot register) rdscur (read security register) wrscur (write security register) wrlr (write lock register) 1st byte 16 (hex) 17 (hex) 18 (hex) 2b (hex) 2f (hex) 2c (hex) 2nd byte e9 (hex) e8 (hex) e7 (hex) d4 (hex) d0 (hex) d3 (hex) 3rd byte 00h 00h 00h 00h 4th byte 00h 00h 00h 00h 5th byte 00h 00h 00h 00h 6th byte 00h 00h 00h 00h 7th byte dummy (note 5) dummy (note 5) data bytes 1-4 (note 8) 4 1 action to read value of security register to set the lock- down bit as "1" (once lock- down, cannot be updated) register commands command (byte) rdsr (read status register) rdcr (read confguration register) wrsr (write status register) wrcr (write confguration register) rdcr2 (read confguration register 2) wrcr2 (write confguration register 2 ) 1st byte 05 (hex) 15 (hex) 01 (hex) 01 (hex) 71 (hex) 72 (hex) 2nd byte fa (hex) ea (hex) fe (hex) fe (hex) 8e (hex) 8d (hex) 3rd byte 00h 00h 00h 00h add1 (note 7) add1 (note 7) 4th byte 00h 00h 00h 00h add2 (note 7) add2 (note 7) 5th byte 00h 00h 00h 00h add3 add3 6th byte 00h 01h 00h 01h add4 (note 7) add4 (note 7) 7th byte dummy (note 5) dummy (note 5) dummy (note 5) data bytes 1 1 1 1 1 1 action to read out the values of the status register to read out the values of the confguration register to write new values of the status register to write new values of the confguration register command (byte) rdlr (read lock register) wrspb (spb bit program) esspb (all spb bit erase) rdspb (read spb status) 1st byte 2d (hex) e3 (hex) e4 (hex) e2 (hex) 2nd byte d2 (hex) 1c (hex) 1b (hex) 1d (hex) 3rd byte 00h add1 add1 4th byte 00h add2 add2 5th byte 00h add3 add3 6th byte 00h add4 add4 7th byte dummy (note 5) dummy (note 4) data bytes 1 1 action MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 21 note 1: it is not recommended to adopt any other code/address not in the command defnition table, which will potentially enter the hidden mode. note 2: before executing rst command, rsten command must be executed. if there is any other command to interfere, the reset operation will be disabled. note 3: the number in parentheses after "add" or "data" stands for how many clock cycles it has. for example, "data(8)" repre - sents there are 8 clock cycles for the data in. note 4: see dummy cycle and frequency table. note 5: 2 dummy cycles in sdr and 4 dummy cycles in dtr. note 6: the starting address must be even byte (a0 must be 0) in dtr opi mode. note 7: the address data must be 00h. note 8: data byte are always output in str. MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 22 9-1. status register status register note 1: see the t able 3 "protected area size". bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved reserved bp3 (level of protected block) bp2 (level of protected block) bp1 (level of protected block) bp0 (level of protected block) wel (write enable latch) wip (write in progress bit) reserved reserved (note 1) (note 1) (note 1) (note 1) 1=write enable 0=not write enable 1=write operation 0=not in write operation reserved reserved non-volatile bit non-volatile bit non-volatile bit non-volatile bit volatile bit volatile bit the defnition of the status register bits is as below: wip bit. the write in progress (wip) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. when wip bit sets to 1, which means the device is busy in program/erase/write status register progress. when wip bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. wel bit. the write enable latch (wel) bit, a volatile bit, indicates whether the device is set to internal write enable latch. when wel bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. when wel bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. the program/erase command will be ignored if it is applied to a protected memory area. to ensure both wip bit & wel bit are both set to 0 and available for next program/erase/operations, wip bit needs to be confrm to be 0 before polling wel bit. after wip bit confrmed, wel bit needs to be confrm to be 0. bp3, bp2, bp1, bp0 bits. the block protect (bp3, bp2, bp1, bp0) bits, non-volatile bits, indicate the protected area (as defned in table 3 ) of the device to against the program/erase instruction without hardware protection mode being set. to write the block protect (bp3, bp2, bp1, bp0) bits requires the write status register (wrsr) instruction to be executed. those bits defne the protected area of the memory to against page program (pp), sector erase (se), block erase 32kb (be32k), block erase (be) and chip erase (ce) instructions (only if block protect bits (bp3:bp0) set to 0, the ce instruction can be executed). the bp3, bp2, bp1, bp0 bits are "0" as default. which is un-protected. MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 23 9-2. confguration register the confguration register is able to change the default status of flash memory. flash memory will be confgured after the cr bit is set. ods bit the output driver strength (ods2, ods1, ods0) bits are volatile bits, which indicate the output driver level (as defned in "output driver strength table" ) of the device. the output driver strength is defaulted as 30 ohms when delivered from factory. to write the ods bits requires the write status register (wrsr) instruction to be executed. tb bit the top/bottom (tb) bit is a non-volatile otp bit. the top/bottom (tb) bit is used to confgure the block protect area by bp bit (bp3, bp2, bp1, bp0), starting from top or bottom of the memory array. the tb bit is defaulted as 0, which means top area protect. when it is set as 1, the protect area will change to bottom area of the memory device. to write the tb bits requires the write status register (wrsr) instruction to be executed. pbe bit the preamble bit enable (pbe) bit is a volatile bit. it is used to enable or disable the preamble bit data pattern output on dummy cycles. the pbe bit is defaulted as 0, which means preamble bit is disabled. when it is set as 1, the preamble bit will be enabled, and inputted into dummy cycles. to write the pbe bits requires the write status register (wrsr) instruction to be executed. confguration register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved reserved reserved pbe (preamble bit enable) tb (top/bottom selected) ods 2 (output driver strength) ods 1 (output driver strength) ods 0 (output driver strength) x x x 0=disable 1=enable 0=top area protect 1=bottom area protect (default=0) (note 1) (note 1) (note 1) x x x volatile bit otp volatile bit volatile bit volatile bit note 1: see 2xwsxw'ulhu6wuhjwk7deoh output driver strength table ods2 ods1 ods0 description note 0 0 0 150 ohms impedance at vcc/2 (typical) 0 0 1 75 ohms 0 1 0 50 ohms 0 1 1 38 ohms 1 0 0 30 ohms 1 0 1 25 ohms 1 1 0 22 ohms 1 1 1 20 ohms (default) MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 24 9-3. confguration register 2 dc [2:0] numbers of dummy cycle octa i/o str (mhz) octa i/o dtr (mhz) 000(default) 20 200 200 001 18 166 166 010 16 166 166 011 14 133 133 100 12 104 104 101 10 104 104 110 8 84 84 111 6 66 66 address bit name description default 000h bit 0 sopi (str opi enable) 0= str opi disable 1= str opi enable 0 bit 1 dopi( dtr opi enable) 0= dtr opi disable 1= dtr opi enable 0 200h bit 0 dqsprc (dtr dqs pre-cycle) 0= 0 cycle 1= 1 cycle 0 bit 1 dos (dqs on str mode) 0= disable 1= enable 0 bit [6:4] dqsskw ( dq to dqs skew) refer to '4wr'466nh7deoh 000 300h bit [2:0] dc (dummy cycle) refer to 'xpp&fohdg)uhtxhf 7deoh0] 000 500h bit 0 psb (pattern select bit) refer to 3uhdpdeoh3dwwhu6hohfw%lw table" 0 options tqsqv (ns,max) tqxqs (ns,max) cl=10pf cl=15pf cl=30pf cl=10pf cl=15pf cl=30pf 001(default) 0 0.2 0.8 1.2 1.4 2 010 -0.2 0 0.6 1.6 1.8 2.4 011 -0.4 -0.2 0.4 2 2.2 2.8 100 -0.4 0.2 2.6 3.2 101 -0.6 0 3 3.6 110 -0.2 4 111 -0.4 4.4 000 0.2 0.4 1 0.8 1 1.6 9-3-1. dq to dqs skew t able 9-3-2. dummy cycle and frequency t able (mhz) all dqs (except dq3) dq3 bit 0=0 0011 0100 1001 1010 0011 0101 0001 0100 bit 0= 1 0101 0101 0101 0101 0101 0101 0101 0101 9-3-3. preamable pattern select bit table note1: a[31:16] are all 0 MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 25 9-4. security register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved e_fail p_fail reserved esb (erase suspend bit) psb (program suspend bit) ldso (indicate if lock-down) secured otp indicator bit - 0=normal erase succeed 1=indicate erase failed (default=0) 0=normal program succeed 1=indicate program failed (default=0) - 0=erase is not suspended 1= erase suspended (default=0) 0=program is not suspended 1= program suspended (default=0) 0 = not lock- down 1 = lock-down (cannot program/ erase otp) 0 = non- factory lock 1 = factory lock - volatile bit volatile bit - volatile bit volatile bit non-volatile bit (otp) non-volatile bit (otp) table 7. security register defnition the defnition of the security register bits is as below: erase fail bit. the erase fail bit is a status fag, which shows the status of last erase operation. it will be set to "1", if the erase operation fails or the erase region is protected. it will be set to "0", if the last operation is successful. please note that it will not interrupt or stop any operation in the fash memory . program fail bit. the program fail bit is a status fag, which shows the status of last program operation. it will be set to "1", if the program operation fails or the program region is protected. it will be set to "0", if the last operation is successful. please note that it will not interrupt or stop any operation in the fash memory . erase suspend bit. erase suspend bit (esb) indicates the status of erase suspend operation. users may use esb to identify the state of fash memory. after the fash memory is suspended by erase suspend command, esb is set to "1". esb is cleared to "0" after erase operation resumes. program suspend bit. program suspend bit (psb) indicates the status of program suspend operation. users may use psb to identify the state of fash memory. after the fash memory is suspended by program suspend command, psb is set to "1". psb is cleared to "0" after program operation resumes. secured otp indicator bit. the secured otp indicator bit shows the chip is locked by factory or not. when it is "0", it indicates non-factory lock; "1" indicates factory-lock. lock-down secured otp (ldso) bit. by writing wrscur instruction, the ldso bit may be set to "1" for customer lock-down purpose. however, once the bit is set to "1" (lock-down), the ldso bit and the 4k-bit secured otp area cannot be updated any more. while it is in 4k-bit secured otp mode, main array access is not allowed. MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 26 9-5. w rite enable (wren) the write enable (wren) instruction is for setting write enable latch (wel) bit. for those instructions like pp, se, be, ce, wrsr, wrcr2, sbl, wrfbr, esfbr, wrscur, wrlr, wspb and esspb which are intended to change the device content wel bit should be set every time after the wren instruction setting the wel bit. the sequence of issuing wren instruction is: cs# goes lowsending wren instruction code cs# goes high. figure 5. write enable (wren) sequence (spi mode) 21 34567 high-z 0 06h command sclk si cs# so figure 6. write enable (wren) sequence (str-opi mode) cs# sclk sio[7:0] 06h f9h figure 7. write enable (wren) sequence (dtr-opi mode) cs# sclk sio[7:0] 06h f9h MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 27 9-6. w rite disable (wrdi) the write disable (wrdi) instruction is to reset write enable latch (wel) bit. the sequence of issuing wrdi instruction is: cs# goes lowsending wrdi instruction codecs# goes high. the wel bit is reset by following situations: - power-up - reset# pin driven low - wrdi command completion - wrsr/wrcr/wrcr2 command completion - pp command completion - se/be/ce command completion - sbl command completion - pgm/ers suspend command completion - softreset command completion - wrscur command completion - wrfbr/esfbr command completion - wrlr/wspb/esspb command completion figure 8. write disable (wrdi) sequence (spi mode) 21 34567 high-z 0 04h command sclk si cs# so figure 9. write disable (wrdi) sequence (str-opi mode) figure 10. write disable (wrdi) sequence (dtr-opi mode) cs# sclk sio[7:0] 04h fbh cs# sclk sio[7:0] 04h fbh MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 28 9-7. read identifcation (rdid) the rdid instruction is for reading the manufacturer id of 1-byte and followed by device id of 2-byte. the macronix manufacturer id and device id are listed as table 8 d defnitions. the sequence o issuing rdd instruction is cs goes low sending rdd instruction code24-bits d data out on so to end rdd operation can drive cs to high at any time during data out. while program/erase operation is in progress, it will not decode the rdid instruction, therefore there's no effect on wkhffohrisurjudphudhrshudwlrklfklfxuuhwolsurjuh:kh&6jrhkljkwkhghlfhldwwdge stage. figure 11. read identifcation (rdid) sequence (spi mode) 21 3456789 command 0 manufacturer identification high-z msb 15 14 13 3210 device identification msb 7 6 5 2 1 0 16 17 18 28 29 30 31 sclk si cs# so 9fh 14 15 10 13 figure 12. read identifcation (rdid) sequence (str-opi mode) figure 13. read identifcation (rdid) sequence (dtr-opi mode) dqs 00 00 mid ty pe pre-drive de nsity dummy address cs# sclk sio[7:0] 9fh 60h 00 00 cs# sclk mid type de nsity pre-drive sio[7:0] 9fh 60h 00 00 00 00 dummy address table 8. id defnitions rdid 9fh manufactory id memory type memory density c2 80 3a MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 29 9-8. read status register (rdsr) the rdsr instruction is for reading status register bits. the read status register can be read at any time (even in program/erase/write status register condition). it is recommended to check the write in progress (wip) bit before sending a new instruction when a program, erase, or write status register operation is in progress. the sequence of issuing rdsr instruction is: cs# goes low sending rdsr instruction code status register data out on so. figure 14. read status register (rdsr) sequence (spi mode) 21 345678 9 10 11 12 13 14 15 command 0 7 6543210 status register out high-z msb 7 6543210 status register out msb 7 sclk si cs# so 05h figure 15. read status register (rdsr) sequence (str-opi mode) figure 16. read status register (rdsr) sequence (dtr-opi mode) sr sr 05h fah cs# sclk pre-drive sio[7:0] 00 00 00 00 dummy address sr sr 05h fah dqs 00 00 pre-drive dummy address cs# sclk sio[7:0] 00 00 MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 30 wr en co mm and program /erase co mm and write progr am data/address (w ri te erase address) rdsr command read array data (same add ress of pgm/ers) program /er ase su ccessfully yes yes program /erase fail no start verify ok? wip=0? progr am /e rase anot her bl ock? prog ram /er ase comp let ed no yes no rds r command* yes wel=1? no * issue rdsr to check bp[3:0]. rdsr command read w el=0, bp[3:0] figure 17. program/erase fow with read array data for user to check if program/erase operation is fnished or not, rdsr instruction fow are shown as follows: MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 31 figure 18. program/erase fow without read array data (read p_fail/e_fail fag) wr en co mm and program /erase co mm and write progr am data/address (w ri te erase address) rdsr command rdscur command program /er ase su ccessfully yes no program /erase fail yes start p_fail/e_fail =1 ? wip=0? progr am /e rase anot her bl ock? prog ram /er ase comp let ed no yes no rds r command* yes wel=1? no * issue rdsr to check bp[3:0]. rdsr command read w el=0, bp[3:0] MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 32 9-9. read confguration register (rdcr) the rdcr instruction is for reading confguration register bits. the read confguration register can be read at any time (even in program/erase/write confguration register condition). the sequence of issuing rdcr instruction is: cs# goes low sending rdcr instruction code confguration register data out on so. figure 19. read confguration register (rdcr) sequence (spi mode) 21 345678 9 10 11 12 13 14 15 command 0 7 6543210 configuration register out high-z msb 7 6543210 configuration register out msb 7 sclk si cs# so 15h figure 20. read confguration register (rdcr) (str-opi mode) figure 21. read confguration register (rdcr) (dtr-opi mode) cr cr 15h eah cs# sclk pre-drive sio[7:0] 00 00 00 01 dummy address cr cr 15h eah 01 dqs 00 00 pre-drive dummy address cs# sclk sio[7:0] 00 MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 33 note : the cs# must go high exactly at 8 bits or 16 bits data boundary to completed the write register command. figure 22. write status register (wrsr) sequence (spi mode) 21 345678 9 10 11 12 13 14 15 status register in configuration register in 0 msb sclk si cs# so 01h high-z command 16 17 18 19 20 21 22 23 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 9-10. w rite status register (wrsr) / write confguration register (wrcr) the wrsr instruction is for changing the values of status register bits and confguration register bits. before sending wrsr instruction, the write enable (wren) instruction must be decoded and executed to set the write enable latch (wel) bit in advance. the wrsr instruction can change the value of block protect (bp3, bp2, bp1, bp0) bits to defne the protected area of memory (as shown in "table 3. protected area sizes" ). the wrsr also can set or reset the status register write disable (srwd) bit, but has no effect on bit1(wel) and bit0 (wip) of the status register. in spi, cs# must go high exactly at the 8 bits or 16 bits data boundary; in dopi, cs# must go high while clock is low; otherwise, the instruction will be rejected and not executed. the self-timed write status register cycle time (tw) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the write status register cycle is in progress. the wip sets 1 during the tw timing, and sets 0 when write status register cycle is completed, and the write enable latch (wel) bit is reset. MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 34 figure 23. write status register (wrsr) sequence (str-opi mode) cs# sclk sio[7:0] 01h feh 00 sr 00 00 00 figure 24. write status register (wrsr) sequence (dtr-opi mode) sr 00 00 cs# sclk sio[7:0] 01h feh 00 00 figure 25. write confguration register (wrcr) sequence (str-opi mode) figure 26. write confguration register (wrcr) sequence (dtr-opi mode) cs# sclk sio[7:0] 01h feh 01 cr 00 00 00 cr 00 00 cs# sclk sio[7:0] 01h feh 00 01 note: cs# must go high while sclk is low. note: cs# must go high while sclk is low. MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 35 figure 27. wrsr fow wr en co mm and wr sr co mm and write status register data rdsr command wrsr successfully yes yes wrsr fail no start verify ok? wip=0? no rds r command yes wel=1? no rds r command read w el=0, bp[3:0] MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 36 9-11. read confguration register 2 (rdcr2) the rdcr2 instruction is for reading confguration register 2. the read confguration register 2 command would be rejected while program/erase/wrsr/wrcr is in progress. the sequence of issuing rdcr2 instruction is: cs# goes low sending rdcr2 instruction code sending 4 byte address confguration register 2 data out on so. note: * see &rjxudwlr5hjlwhu for defning address . figure 28. read confguration register 2 (rdcr2) sequence (spi mode) figure 29. read confguration register 2 (rdcr2) sequence (str-opi mode) figure 30. read confguration register 2 (rdcr2) (dtr-opi mode) cs# sclk cr2 cr2 pre-drive sio[7:0] 71h 8eh 00 00 a[15:8] a[7:0] dummy addres s * cr2 cr2 dqs 00 00 pre-drive dummy addres s * cs# sclk sio[7:0] 71h 8eh a[15:8] a[7:0] note: * see &rjxudwlr5hjlwhu for defning address . sclk si cs# so 7654 3 1 7 0 cr2 cr2 msb msb 2 71h high-z command address * 31 30 29 0123 note: * see &rjxudwlr5hjlwhu for defning address . MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 37 9-12. w rite confguration register 2 (wrcr2) the wrcr2 instruction is for changing the values of confguration register 2. before sending wrcr2 instruction, the write enable (wren) instruction must be decoded and executed to set the write enable latch (wel) bit in advance. in spi, cs# must go high exactly at the 8 bits data boundary; in dopi, cs# must go high while clock is low; otherwise, the instruction will be rejected and not executed, and the write enable latch (wel) bit is reset. cs# sclk sio[7:0] 72h 8dh cr2 00 00 addres s * a[15:8] a[7:0] cr2 00 00 cs# sclk sio[7:0] 72h 8dh addres s * a[15:8] a[7:0] note 1: * see &rjxudwlr5hjlwhu for defning address . note 1 : * see &rjxudwlr5hjlwhu for defning address. note 2 : cs# must go high while sclk is low figure 31. write confguration register 2 (wrcr2) sequence (spi mode) figure 32. write confguration register 2 (wrcr2) sequence (str-opi mode) figure 33. write confguration register 2 (wrcr2) sequence (dtr-opi mode) 76543 2 0 1 cr2 msb msb sclk cs# si 72h command address * 31 30 29 23 1 0 note 1: * see &rjxudwlr5hjlwhu for defning address . MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 38 9-13. read security register (rdscur) the rdscur instruction is for reading the value of security register bits. the read security register can be read at any time (even in program/erase/write status register/write security register condition) and continuously. the sequence of issuing rdscur instruction is : cs# goes lowsending rdscur instructionsecurity register data out on so cs# goes high. figure 34. read security register (rdscur) sequence (spi mode) 21 345678 9 10 11 12 13 14 15 command 0 7 6543210 security register out high-z msb 7 6543210 security register out msb 7 sclk si cs# so 2bh figure 35. read security register (rdscur) sequence (str-opi mode) figure 36. read security register (rdscur) sequence (dtr-opi mode) security register security register 2bh d4h cs# sclk pre-drive sio[7:0] 00 00 00 00 dummy address 2bh d4h security register security register dqs 00 00 pre-drive dummy address cs# sclk sio[7:0] 00 00 MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 39 9-14. w rite security register (wrscur) the wrscur instruction sets the ldso bit of the security register. the wren (write enable) instruction is required before issuing wrscur instruction. the wrscur instruction may change the values of bit1 (ldso bit) for customer to lock-down the 4k-bit secured otp area. once the ldso bit is set to "1", the secured otp area cannot be updated any more. the sequence of issuing wrscur instruction is :cs# goes low sending wrscur instruction cs# goes high. the cs# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. figure 37. write security register (wrscur) sequence (spi mode) 2fh 21 34567 high-z 0 command sclk si cs# so figure 38. write security register (wrscur) sequence (str-opi mode) figure 39. write security register (wrscur) sequence (dtr-opi mode) cs# sclk sio[7:0] 2fh d0h cs# sclk sio[7:0] 2fh d0h MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 40 9-15. read data bytes (read) the read instruction is for reading data out. the address is latched on rising edge of sclk, and data shifts out on the falling edge of sclk at a maximum frequency fr. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing read instruction is: cs# goes lowsending read instruction code 4-byte address on si data out on soto end read operation can use cs# to high at any time during data out. figure 40. read data bytes (read) sequence (spi mode only) sclk si cs# so 7654 3 1 7 0 data out 1 msb msb 2 data out 2 13h high-z command 32-bit address 31 30 29 0123 MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 41 9-16. read data bytes at higher speed (f ast_read) the fast_read instruction is for quickly reading data out. the address is latched on rising edge of sclk, and data of each bit shifts out on the falling edge of sclk at a maximum frequency fc. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single fast_read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing fast_read instruction is: cs# goes low sending fast_read instruction code 4-byte address on si 8 dummy cycles data out on so to end fast_read operation can use cs# to high at any time during data out. while program/erase/write status register cycle is in progress, fast_read instruction is rejected without any impact on the program/erase/write status register current cycle. figure 41. read at higher speed (fast_read) sequence (spi mode only) high-z 76543 2 0 1 data out 1 dummy cycle msb 7 6543210 data out 2 msb msb 7 76543 2 0 1 sclk si cs# so sclk si cs# so 0ch 31 30 29 0123 command 32-bit address MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 42 9-17. oct a read mode (8read) the 8read instruction enable octa throughput of serial flash in read mode. an opi enable bit of confguration register 2 must be set to "1" before sending the str octa read instruction. while program/erase/write status register cycle is in progress, 8read instruction is rejected without any impact on the program/erase/write status register current cycle. figure 42. octa read mode sequence (str-opi mode) a[31:24] a[23:16] a[15:8] a[7:0] d1 d0 cs# sclk pre-drive sio[7:0] ech 13h dummy address d3 d2 MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 43 9-18. oct a dtr read mode (8dtrd) the 8dtrd instruction enable dtr octa throughput of serial flash in read mode. an dopi enable bit of confguration register 2 must be set to "1" before sending the dtr octa read instruction. while program/erase/write status register cycle is in progress, 8dtrd instruction is rejected without any impact on the program/erase/write status register current cycle. in dtr octa read mode, the starting address must be even byte (a0=0). figure 43. octa read mode sequence (dtr-opi mode) cs# sclk dqs dummy sio[7:0] eeh 11h d3 d2 d1 d0 word unit word unit address a[31:24]a[23:16] a[15:8] a[7:0] MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 44 9-19. preamble bit the preamble bit data pattern supports system/memory controller to determine the valid windows of data output more easily and improve data capture reliability while the fash memory is running in high frequency . the preamble bit is designed as a 16-bit data pattern, which can be enabled or disabled by setting the bit4 of confguration register (preamble bit enable bit). once cr<4> is set, the preamble bit is inputted into dummy cycles. two different patterns are selectable by setting cr<2> psb (pattern select bit), and please refer to "9-3. confguration register 2" for details. once preamble bit feature is enabled, the preamble bit pattern will be output after a pre-driven signal. when the device is under opi mode, all sio pins except sio3 will output the same learning pattern. the signal on sio3 will be different from other i/o pins in case psb=0. when dummy cycle number reaches 18, the complete 16 bits will start to output right after the pre-driven signal. when dummy cycle number is not suffcient of 16 cycles, the rest of the preamble bits will be cut of f. dlp1 dlp0 cs# sclk pre-drive sio[7:0] ech 13h dummy address dlp3 dlp2 d[7:0] d[7:0] a[ 7:0] a[31 :24] a[2 3:16] a[15:8] figure 44. preamble bit data pattern output sequence (str-opi mode) dqs pre-drive dummy address cs# sclk sio[7:0] eeh 11h dlp1 dlp0 dlp3 dlp2 d[7:0] d[7:0] d[7:0] d[7:0] a [7:0] a [31 :24] a [2 3:16] a [15:8] figure 45. preamble bit data pattern output sequence (dtr-opi mode) note: 6 dummy cycle example. note: 6 dummy cycle example. MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 45 the wrap around unit is defned within the 256byte page, with random initial address. it is defned as wrap-around mode disable for the default state of the device. to exit wrap around, it is required to issue another c0 command in which data=1xh. otherwise, wrap around status will be retained until power down or reset command. to change wrap around depth, it is requried to issue another c0 command in which data=0xh. burst read is supported in both spi and opi mode after wrap around is enable. the device is default without burst read. data wrap around wrap depth 00h reserved reserved 01h yes 16-byte 02h yes 32-byte 03h yes 64-byte 1xh no x 0 cs# sclk sio c0h d7 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 6 7 8 9 10 1 12 13 14 15 5 figure 46. set burst length (spi mode) 9-20. burst read t o set the burst length, following command operation is required to issue command: c0h in the frst byte, following 4 clocks defning wrap around enable with 0h and disable with1h. the next 4 clocks are to defne wrap around depth. their defnitions are as the following table: figure 47. set burst length (str-opi mode) figure 48. set burst length (dtr-opi mode) cs# sclk sio[7:0] c0h 3fh 00 sbl 00 00 00 sbl 00 00 cs# sclk sio[7:0] c0h 3fh 00 00 note: in dopi, cs# pin must go high while sclk pin is low. MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 46 fast boot register (fbr) 9-21. fast boot the fast boot feature provides the ability to automatically execute read operation after power on cycle or reset without any read instruction. a fast boot register is provided on this device. it can enable the fast boot function and also defne the number of delay cycles and start address (where boot code being transferred). instruction wrfbr (write fast boot register) and esfbr (erase fast boot register) can be used for the status confguration or alternation of the fast boot register bit. rdfbr (read fast boot register) can be used to verify the program state of the fast boot register. the default number of delay cycles is 20 cycles, and there is a 16bytes boundary address for the start of boot code access. when cs# starts to go low, data begins to output from default address after the delay cycles. after cs# returns to go high, the device will go back to standard spi/opi/dopi mode and user can start to input command. in the fast boot data out process from cs# goes low to cs# goes high, a minimum of one byte must be output. once fast boot feature has been enabled, the device will automatically start a read operation after power on cycle, reset command, or hardware reset operation. bits description bit status default state type 31 to 4 fbsa (fastboot start address) 16 bytes boundary address for the start of boot code access. fffffff non- volatile 3 reserved 1 non- volatile 2 to 1 fbsd (fastboot start delay cycle) 00: 11 delay cycles 01: 15 delay cycles 10: 17 delay cycles 11: 21 delay cycles 11 non- volatile 0 fbe (fastboot enable) 0=fastboot is enabled. 1=fastboot is not enabled. 1 non- volatile figure 49. fast boot sequence (spi mode) n+2 delay cycles 0 7 6543210 data out 1 high impedance msb 7 6543210 data out 2 msb 7 sclk si cs# so - - - - - - n n+1 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14 n+15 don?t care or high impedance msb note: the delay cycle is always 13 in spi mode. MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 47 figure 50. fast boot sequence (str-opi mode) d1 d0 cs# sclk pre-drive sio[7:0] delay cycles d3 d2 figure 51. fast boot sequence (dtr-opi mode) d0 d1 dqs pre-drive delay cycles cs# sclk sio[7:0] note: if fbsd = 1 1, delay cycles is 21 and n is 20. if fbsd = 10, delay cycles is 17 and n is 16. if fbsd = 01, delay cycles is 15 and n is 14. if fbsd = 00, delay cycles is 1 1 and n is 10. note: if fbsd = 1 1, delay cycles is 21 and n is 20. if fbsd = 10, delay cycles is 17 and n is 16. if fbsd = 01, delay cycles is 15 and n is 14. if fbsd = 00, delay cycles is 1 1 and n is 10. MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 48 figure 52. read fast boot register (rdfbr) sequence 21 3456789 0 sclk cs# si so 16h command 37 10 38 39 40 41 msb 7 6 7 6 5 25 2426 high-z msb data out 1 data out 2 figure 53. read fast boot register (rdfbr) sequence (str-opi mode) figure 54. read fast boot register (rdfbr) sequence (dtr-opi mode) fbr2 fbr1 cs# sclk pre-drive sio[7:0] 16h e9h 00 00 00 00 dummy address fbr1 fbr2 dqs 00 00 pre-drive dummy address cs# sclk sio[7:0] 16h e9h 00 00 MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 49 figure 55. write fast boot register (wrfbr) sequence 21 3456789 0 msb sclk cs# si 17h command 37 38 39 fast boot register so high-z 7 6 25 2426 10 5 figure 56. write fast boot register (wrfbr) sequence (str-opi mode) figure 57. write fast boot register (wrfbr) sequence (dtr-opi mode) cs# sclk sio[7:0] 17h e8h 00 fbr1 fbr4 00 00 00 00 00 00 00 fbr1 fbr2 fbr3 fbr4 17h e8h cs# sclk sio[7:0] MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 50 figure 58. erase fast boot register (esfbr) sequence 21 34567 high-z 0 18h command sclk si cs# so figure 59. erase fast boot register (esfbr) sequence (str-opi mode) figure 60. erase fast boot register (esfbr) sequence (dtr-opi mode) cs# sclk sio[7:0] 18h e7h cs# sclk sio[7:0] 18h e7h MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 51 figure 61. sector erase (se) sequence (spi mode) 31 30 2 1 0 msb sclk cs# si 21h command 32-bit address 9-22. sector erase (se) the sector erase (se) instruction is for erasing the data of the chosen sector to be "1". the instruction is used for any 4k-byte sector. a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the sector erase (se). any address of the sector (see "table 2. memory organization" ) is a valid address for sector erase (se) instruction. the cs# must go high exactly at the byte boundary (the least signifcant bit of the address byte been latched-in); otherwise, the instruction will be rejected and not executed. the sequence of issuing se instruction is: cs# goes low sending se instruction code 4-byte address cs# goes high. the self-timed sector erase cycle time (tse) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked while the sector erase cycle is in progress. the wip sets 1 during the tse timing, and clears when sector erase cycle is completed, and the write enable latch (wel) bit is cleared. if the block is protected by bp bits (block protect mode), the sector erase (se) instruction will not be executed on the block. figure 62. sector erase (se) sequence (str-opi mode) figure 63. sector erase (se) sequence (dtr-opi mode) a[ 7:0] a[31 :24] a[2 3:16] a[15:8] cs# sclk sio[7:0] 21h deh cs# sclk sio[7:0] 21h deh a [7:0] a [31 :24] a [2 3:16] a [15:8] MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 52 9-23. block erase (be) the block erase (be) instruction is for erasing the data of the chosen block to be "1". the instruction is used for 64k-byte block erase operation. a write enable (wren) instruction must be executed to set the write enable latch (wel) bit before sending the block erase (be). any address of the block (please refer to "table 2. memory organization" ) is a valid address for block erase (be) instruction. the cs# must go high exactly at the byte boundary (the least signifcant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed. the sequence of issuing be instruction is: cs# goes low sending be instruction code 4-byte address cs# goes high. the self-timed block erase cycle time (tbe) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked while the block erase cycle is in progress. the wip sets during the tbe timing, and clears when block erase cycle is completed, and the write enable latch (wel) bit is reset. if the block is protected by bp bits (block protect mode), the block erase (be) instruction will not be executed on the block. figure 64. block erase (be) sequence (spi mode) msb sclk cs# si dch command 32-bit address 31 30 2 1 0 figure 65. block erase (be) sequence (str-opi mode) figure 66. block erase (be) sequence (dtr-opi mode) cs# sclk sio[7:0] dch 23h a [7:0] a [31 :24] a [2 3:16] a [15:8] a[ 7:0] a[31 :24] a[2 3:16] a[15:8] cs# sclk sio[7:0] dch 23h MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 53 9-24. chip erase (ce) the chip erase (ce) instruction is for erasing the data of the whole chip to be "1". a write enable (wren) instruction must be executed to set the write enable latch (wel) bit before sending the chip erase (ce). the cs# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not executed. the sequence of issuing ce instruction is: cs# goes lowsending ce instruction codecs# goes high. the self-timed chip erase cycle time (tce) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked while the chip erase cycle is in progress. the wip sets during the tce timing, and clears when chip erase cycle is completed, and the write enable latch (wel) bit is cleared. when the chip is under "block protect (bp) mode". the chip erase (ce) instruction will not be executed, if one (or more) sector is protected by bp3-bp0 bits. it will be only executed when bp3-bp0 all set to "0". figure 67. chip erase (ce) sequence (spi mode) 21 34567 0 60h or c7h sclk si cs# command figure 68. chip erase (ce) sequence (str-opi mode) figure 69. chip erase (ce) sequence (dtr-opi mode) 60h or c7h 9fh or 38h cs# sclk sio[7:0] 60h or c7h 9fh or 38h cs# sclk sio[7:0] MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 54 9-25. page program (pp) the page program (pp) instruction is for programming the memory to be "0". a write enable (wren) instruction must be executed to set the write enable latch (wel) bit before sending the page program (pp). the device programs only the last 256 data bytes sent to the device. the last address byte (the 8 least signifcant address bits, a7-a0) should be set to 0 for 256 bytes page program. if a7-a0 are not all zero, transmitted data that exceed page length are programmed from the starting address (32-bit address that last 8 bit are all 0) of currently selected page. if the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page and previous data will be disregarded. if the data bytes sent to the device has not exceeded 256, the data will be programmed at the request address of the page. there will be no effort on the other data bytes of the same page. in dtr opi, the starting address given must be even address (a0=0) and data byte number must be even. the sequence of issuing pp instruction is: cs# goes low sending pp instruction code 4-byte address at least 1-byte on data in spi and str opi; at least two bytes in dopi cs# goes high. the cs# must be kept to low during the whole page program cycle; the cs# must go high exactly at the byte boundary in spi (the latest eighth bit of data being latched in), cs# must go high while sclk is low in dopi, otherwise the instruction will be rejected and will not be executed. the self-timed page program cycle time (tpp) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked while the page program cycle is in progress. the wip sets during the tpp timing, and clears when page program cycle is completed, and the write enable latch (wel) bit is cleared. if the page is protected by bp bits (block protect mode), the page program (pp) instruction will not be executed. figure 70. page program (pp) sequence (spi mode) 76543 2 0 1 data byte 1 76543 2 0 1 data byte 2 76543 2 0 1 data byte 3 data byte 256 76543 2 0 1 msb msb msb msb msb sclk cs# si sclk cs# si 02h command 32-bit address 31 30 29 23 1 0 MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 55 figure 71. page program (pp) sequence (str-opi mode) figure 72. page program (pp) sequence (dtr-opi mode) tchsh ts lch 02h fdh a[31:24] a[23:16] a[15:8] a[7:0 ] d0 d1 d254 d255 cs# sclk sio[7:0] cs# sclk tslch tclsh word unit word unit sio[7:0] 02h d1 d0 d255 d254 fdh a [7:0] a [31 :24] a [2 3:16] a [15:8] MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 56 9-26. deep power-down (dp) the deep power-down (dp) instruction is for setting the device to minimum power consumption (the standby current is reduced from isb1 to isb2). the deep power-down mode requires the deep power-down (dp) instruction to enter, during the deep power-down mode, the device is not active and all write/program/erase instruction are ignored. when cs# goes high, it's only in deep power-down mode not standby mode. it's different from standby mode. the sequence of issuing dp instruction is: cs# goes lowsending dp instruction codecs# goes high. once the dp instruction is set, all instruction will be ignored except the release from deep power-down mode (rdp) and read electronic signature (res) instruction and softreset command. (those instructions allow the id being reading out). when power-down, or software reset command the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. for dp instruction the cs# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. as soon as chip select (cs#) goes high, a delay of tdp is required before entering the deep power-down mode. figure 73. deep power-down (dp) sequence (spi mode) 21 34567 0 t dp deep power-down mode stand-by mode sclk cs# si b9h command figure 74. deep power-down (dp) sequence (str-opi mode) figure 75. deep power-down (dp) sequence (dtr-opi mode) tdp stand-by mode deep power-down mode b9h 46h cs# sclk sio[7:0] tdp b9h 46h stand-by mode deep power-down mode cs# sclk sio[7:0] MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 57 9-27. release from deep power-down (rdp) the release from deep power-down (rdp) instruction is completed by driving chip select (cs#) high. when chip select (cs#) is driven high, the device is put in the stand-by power mode. if the device was not previously in the deep power-down mode, the transition to the stand-by power mode is immediate. if the device was previously in the deep power-down mode, though, the transition to the stand-by power mode is delayed by tres2, and chip select (cs#) must remain high for at least tres2(max), as specifed in table 15 ac characteristics. once in the stand-by power mode, the device waits to be selected, so that it can receive, decode and execute instructions. the rdp instruction is only for releasing from deep power down mode. reset# pin goes low will release the flash from deep power down mode. even in deep power-down mode, the rdp is also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress. figure 76. release from deep power-down (rdp) sequence (spi mode) 21 34567 0 t res1 stand-by mode deep power-down mode high-z sclk cs# si so abh command figure 77. release from deep power-down (rdp) sequence (str-opi mode) figure 78. release from deep power-down (rdp) sequence (dtr-opi mode) cs# sclk sio[7:0] abh tres1 54h stand-by mode deep power-down mode cs# sclk sio[7:0] tres1 stand-by mode deep power-down mode abh 54h MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 58 9-28. enter secured otp (enso) the enso instruction is for entering the additional 4k-bit secured otp mode. while device is in 4k-bit secured otpmode, main array access is not available. the additional 4k-bit secured otp is independent from main array and may be used to store unique serial number for system identifer. after entering the secured otp mode, follow standard read or program procedure to read out the data or update data. the secured otp data cannot be updated again once it is lock-down. the sequence of issuing enso instruction is: cs# goes low sending enso instruction to enter secured otp mode cs# goes high. please note that after issuing enso command user can only access secure otp region with standard read or program procedure. furthermore, once security otp is lock down, only read related commands are valid. 9-29. exit secured otp (exso) the exso instruction is for exiting the additional 4k-bit secured otp mode. the sequence of issuing exso instruction is: cs# goes low sending exso instruction to exit secured otp mode cs# goes high. MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 59 9-30. individual sector protection there is a non-volatile (spb) protection bit related to the single sector in main fash array. each of the sectors is protected from programming or erasing operation when the bit is set. the fgure below helps describing an overview of these methods. the device is default to the solid mode when shipped from factory. the detail algorithm of advanced sector protection is shown as follows: figure 79. individual sector protection overview start set spb lock bit ? spblkdn = 0 spblkdn = 1 spb lock bit unlocked spb is changeable spb access register (spb) spb=1 write protect spb=0 write unprotect spb 0 spb 1 spb 2 : : spb n-1 spb n sa 0 sa 1 sa 2 : : sa n-1 sa n spb lock bit locked all spb can not be changeable sector array MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 60 9-30-1. lock register the lock register is a 8-bit one-time programmable register . lock register bit [6] is spb lock down bit (spblkdn) which is an unique bit assigned to control all spb bit status. when spblkdn is 1, spb can be changed. when it is locked as 0, all spb can not be changed anymore, and spblkdn bit itself can not be altered anymore, either. the lock register is programmed using the wrlr (write lock register) command. a wren command must be executed to set the wel bit before sending the wrlr command. lock register bits field name function type default state description 7 rfu reserved otp 1 reserved for future use 6 spblkdn spb lock down otp 1 1 = spb changeable 0 = freeze spb 5 to 0 rfu reserved otp 1 reserved for future use figure 80. read lock register (rdlr) sequence 21 345678 9 10 11 12 13 14 15 command 0 7 6543210 high-z msb register out 7 sclk si cs# so 2dh figure 81. read lock register (rdlr) sequence (str-opi mode) 2dh d2h lr lr cs# sclk pre-drive sio[7:0] 00 00 00 00 dummy address MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 61 figure 82. read lock register (rdlr) sequence (dtr-opi mode) 2dh d2h lr lr dqs 00 00 pre-drive dummy address cs# sclk sio[7:0] 00 00 figure 83. write lock register (wrlr) sequence 21 345678 9 10 11 12 13 14 15 lock register in 0 msb sclk si cs# so 2ch high-z command 7 6 5 4 3 2 1 0 lr 00 00 cs# sclk sio[7:0] 2ch d3h 00 00 figure 84. write lock register (wrlr) sequence (str-opi mode) figure 85. write lock register (wrlr) sequence (dtr-opi mode) cs# sclk sio[7:0] 2ch d3h 00 lr 00 00 00 note: cs# must go high while sclk is low. MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 62 9-30-2. solid protection bits the solid protection bits (spbs) are nonvolatile bits for enabling or disabling write-protection to sectors and blocks. the spb bits have the same endurance as the flash memory. an spb is assigned to each 4kb sector in the bottom and top 64kb of memory and to each 64kb block in the remaining memory. the factory default state of the spb bits is 0, which has the sector/block write-protection disabled. when an spb is set to 1, the associated sector or block is write-protected. program and erase operations on the sector or block will be inhibited. spbs can be individually set to 1 by the wrspb command. however, the spbs cannot be individually cleared to 0. issuing the esspb command clears all spbs to 0. a wren command must be executed to set the wel bit before sending the wrspb or esspb command. the rdspb command reads the status of the spb of a sector or block. the rdspb command returns 00h if the spb is 0, indicating write-protection is disabled. the rdspb command returns ffh if the spb is 1, indicating write-protection is enabled. note: if spblkdn=0, commands to set or clear the spb bits will be ignored. spb register bit description bit status default type 7 to 0 spb (solid protection bit) 00h = unprotect sector / block ffh = protect sector / block 00h non-volatile MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 63 figure 86. read spb status (rdspb) sequence 21 3456789 0 msb sclk cs# si so e2h command mode 3 37 38 39 40 41 42 mode 0 32-bit address a31 a30 a2 a1 a0 7 6543210 high-z msb data out 43 44 45 46 47 figure 87. read spb status (rdspb) sequence (str-opi mode) a[31:24] a[23:16] a[15:8] a[7:0] spb spb cs# sclk pre-drive sio[7:0] e2h 1dh dummy address figure 88. read spb status (rdspb) sequence (dtr-opi mode) spb spb dqs pre-drive dummy addres s cs# sclk sio[7:0] e2h 1dh a [15:8] a [7:0] a [31:24] a [23:16] MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 64 figure 89. spb erase (esspb) sequence 21 34567 high-z 0 e4h command sclk si cs# so figure 90. spb erase (esspb) sequence (str-opi mode) figure 91. spb erase (esspb) sequence (dtr-opi mode) e4h 1bh cs# sclk sio[7:0] cs# sclk sio[7:0] e4h 1bh MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 65 figure 92. spb program (wrspb) sequence 21 3456789 0 msb sclk cs# si e3h command 37 38 39 32-bit address a31 a30 a2 a1 a0 figure 93. spb program (wrspb) sequence (str-opi mode) figure 94. spb program (wrspb) sequence (dtr-opi mode) cs# sclk sio[7:0] e3h 1ch a [7:0] a [31 :24] a [2 3:16] a [15:8] a[ 7:0] a[31 :24] a[2 3:16] a[15:8] cs# sclk sio[7:0] e3h 1ch MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 66 9-31. program/erase suspend/resume the device allow the interruption of sector-erase, block-erase or page-program operations and conduct other operations. after issue suspend command, the system can determine if the device has entered the erase-suspended mode through bit2 (psb) and bit3 (esb) of security register. (please refer to "table 7. security register defnition" ) 9-32. erase suspend erase suspend allow the interruption of all erase operations. after the device has entered erase-suspended mode, the system can read any sector(s) or block(s) except those being erased by the suspended erase operation. reading the sector or block being erase suspended is invalid. after erase suspend, wel bit will be clear, following commands can be accepted. (including: 13h, 0ch, ech, eeh, 5ah, c0h, 06h, 04h, 2bh, 9fh, 05h, abh, 02h, 38h, b0h, 30h, 66h, 99h, 00h, 15h, 16h, 13h, 0ch, ech, 2dh, e2h) erase suspend bit (esb) indicates the status of erase suspend operation. users may use esb to identify the state of fash memory. after the fash memory is suspended by erase suspend command, esb is set to "1". esb is cleared to "0" after erase operation resumes. 9-33. program suspend prog ram suspend allows the interruption of all program operations. after the device has entered program- suspended mode, the system can read any sector(s) or block(s) except those be ing programmed by the suspended program operation. reading the sector or block being program suspended is invalid. after program suspend, wel bit will be cleared, only read related, resume and reset command can be accepted. (including: 13h, 0ch, ech, eeh, 5ah, c0h, 06h, 04h, 2bh, 9fh, 05h, abh, b0h, 30h, 66h, 99h, 00h, 15h, 16h, 13h, 0ch, ech, 2dh, e2h) program suspend bit (psb) indicates the status of program suspend operation. users may use psb to identify the state of fash memory. after the fash memory is suspended by program suspend command, psb is set to "1". psb is cleared to "0" after program operation resumes. MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 67 figure 95. suspend to read/program latency cs# suspend command read/program command tpsl / tesl tpsl: program latency tesl: erase latency figure 96. resume to read latency cs# tse / tbe / tpp resume command read command figure 97. resume to suspend latency cs# resume command suspend command tprs / ters tprs: program resume to another suspend ters: erase resume to another suspend MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 68 9-34. w rite-resume the write operation is being resumed when write-resume instruction issued. esb or psb (suspend status bit) in status register will be changed back to 0. the operation of write-resume is as follows: cs# drives low send write resume command cycle (30h) drive cs# high. by polling busy bit in status register, the internal write operation status could be checked to be completed or not. the user may also wait the time lag of tse, tbe, tpp for sector-erase, block-erase or page-programming. wren (command "06") is not required to issue before resume. resume to another suspend operation requires latency time of 100us (from program suspend resume)/200us (from erase suspend resume). please note that, if "performance enhance mode" is executed during suspend operation, the device can not be resume. to restart the write command, disable the "performance enhance mode" is required. after the "performance enhance mode" is disable, the write-resume command is effective. 9-35. no operation (nop) the no operation command is only able to terminate the reset enable (rsten) command and will not affect any other command. 9-36. software reset (reset-enable (rsten) and reset (rst)) the software reset operation combines two instructions: reset-enable (rsten) command following a reset (rst) command. it returns the device to a standby mode. all the volatile bits and settings will be cleared then, which makes the device return to the default status as power on. to execute reset command (rst), the reset-enable (rsten) command must be executed frst to perform the reset operation. if there is any other command to interrupt after the reset-enable command, the reset-enable will be invalid. if the reset command is executed during program or erase operation, the operation will be disabled, the data under processing could be damaged or lost. the reset time is different depending on the last operation. for details, please refer to "table 11. reset timing- (other operation)" for tready2. MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 69 figure 98. software reset recovery cs# mode 66 99 stand-by mode tready2 figure 99. reset sequence (spi mode) cs# sclk sio0 66h 99h command command t shsl figure 100. reset sequence (str-opi mode) note: refer to "table 11. reset timing-(other operation)" for tready2. figure 101. reset sequence (dtr-opi mode) cs# sclk sio[7:0] 66h 66h 99h 99h t shsl cs# sclk sio[7:0] 66h 66h 99h 99h t shsl MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 70 9-37. read sfdp mode (rdsfdp) the serial flash discoverable parameter (sfdp) standard provides a consistent method of describing the functional and feature capabilities of serial fash devices in a standard set of internal parameter tables. these parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. the concept is similar to the one found in the introduction of jedec standard, jesd68 on cfi. the sequence of issuing rdsfdp instruction in spi is cs# goes lowsend rdsfdp instruction (5ah)send 3 address bytes on si pinread sfdp code on soto end rdsfdp operation can use cs# to high at any time during data out. sfdp in spi is a jedec standard, jesd216. the sequcn of issuing rdsfdp instruction in opi/dopi mode: cs# low send rdsfdp instruction (5ah/a5h) send 4 address bytes on sio pin send 20 dummy byte read sfdp code on sio[7:0] to end rdsfdp operation can use cs# to high at any time during data out. figure 102. read serial flash discoverable parameter (rdsfdp) sequence 23 21 345678 9 10 28 29 30 31 22 21 3210 high-z 24 bit address 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 76543 2 0 1 data out 1 dummy cycle msb 7 6543210 data out 2 msb msb 7 47 76543 2 0 1 35 sclk si cs# so sclk si cs# so 5ah command MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 71 figure 103. octa read mode sequence (str-opi mode) table 9. signature and parameter identifcation data values (tbd) a[31:24] a[23:16] a[15:8] a[7:0] d1 d2 d0 27 26 1 2 3 4 5 6 28 cs# sclk pre-drive sio[7:0] 5ah a5h dummy address note: address must be low byte (a0=0) in dtr opi. MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 72 10. reset driving the reset# pin low for a period of trlrh or longer will reset the device. after reset cycle, the device is at the following states: - standby mode - all the volatile bits such as wel/wip will return to the default status as power on. - all the volatile bits in cr2 will return to the default status as power on. if the device is under programming or erasing, driving the rese t# pin low will also terminate the operation and data could be lost. during the resetting cycle, the sio data becomes high impedance and the current will be reduced to minimum. symbol parameter min. typ. max. unit trhsl reset# high before cs# low 10 us trs reset# setup time 15 ns trh reset# hold time 15 ns trlrh reset# low pulse width 10 us tready1 reset recovery time 35 us figure 104. reset timing table 10. reset timing-(power on) symbol parameter min. typ. max. unit trhsl reset# high before cs# low 10 us trs reset# setup time 15 ns trh reset# hold time 15 ns trlrh reset# low pulse width 10 us tready2 reset recovery time (during instruction decoding) 40 us reset recovery time (for read operation) 40 us reset recovery time (for program operation) 310 us reset recovery time(for se4kb operation) 12 ms reset recovery time (for be64k/be32kb operation) 25 ms reset recovery time (for chip erase operation) 100 ms reset recovery time (for wrsr operation) 40 ms table 11. reset timing-(other operation) trhsl trs trh trlrh tready1 / tready2 sclk reset# cs# MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 73 11. power-on state the device is at below states when power-up: - standby mode (please n ote it is not deep power-down mode) - w rite enable latch (wel) bit is reset the device must not be selected during power-up and power-down stage unless the vcc achieves below correct level: - vcc minimum at power- up stage and then after a delay of tvsl - gnd at power-down please note that a pull-up resistor on cs# may ensure a safe and proper power-up/down level. an internal power-on reset (por) circuit may protect the device from data corruption and inadvertent data change during power up state. when vcc is lower than vwi (por threshold voltage value), the internal logic is reset and the fash device has no response to any command. for further protection on the device, if the vcc does not reach the vcc minimum level, the correct operation is not guaranteed. the write, erase, and program command should be sent after the below time delay: - tvsl after vcc reached vcc minimum level the device can accept read command after vcc reached vcc minimum and a time delay of tvsl. please refer to the " "power-up timing" ". note: - to stabilize the vcc level, the vcc rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1uf) - at power-down stage, the vcc drops below vwi level, all operations are disable and device has no response to any command. the data corruption might occur during the stage while a write, program, erase cycle is in progress. - to stabilize the vccq level, the vccq/vssq rail decoupled by a suitable capacitor close to package pins is recommended. - it is recommended vcc/gnd vccq/vssq power are separated system supply with same supply voltage. MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 74 12. electrical specifications figure 105. maximum negative overshoot waveform figure 106. maximum positive overshoot waveform 0v -1.0v 20ns vcc+1.0v 2.0v 20ns notice: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only and functional operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended period may affect reliability. 2. specifcations contained within the following tables are subject to change. 3. during voltage transitions, all pins may overshoot to vcc+1.0v or -1.0v for period up to 20ns. t able 12. absolute maximum ratings rating value ambient operating temperature industrial grade -40c to 85c storage temperature -65c to 150c applied input voltage -0.5v to vcc+0.5v applied output voltage -0.5v to vcc+0.5v vcc to ground potential -0.5v to 2.5v table 13. capacitance ta = 25c, f = 1.0 mhz symbol parameter min. typ. max. unit conditions cin input capacitance 16 pf vin = 0v cout output capacitance 16 pf vout = 0v MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 75 figure 107. input test waveforms and measurement level figure 108. output loading ac measurement level input timing reference level output timing reference level 0.8vcc 0.7vcc 0.3vcc 0.5vcc 0.2vcc note: input pulse rise and fall time are <5ns device under test cl 25k ohm 25k ohm +1.8v cl=30pf including jig capacitance MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 76 table 14. dc characteristics notes : 1. t ypical values at vcc = 1.8v, t = 25 c. these currents are valid for all product versions (package and speeds). 2. t ypical value is calculated by simulation. symbol parameter notes min. typ. max. units test conditions ili input load current 1 2 ua vcc = vcc max, vin = vcc or gnd ilo output leakage current 1 2 ua vcc = vcc max, vout = vcc or gnd isb1 vcc standby current 1 20 100 ua vin = vcc or gnd, cs# = vcc isb2 deep power-down current 5 20 ua vin = vcc or gnd, cs# = vcc icc1 vcc read 1 15 25 ma 200mhz 8io str (dq foating) 25 35 ma 200mhz 8io dtr (dq foating) icc2 vcc program current 1 40 60 ma program in progress, cs# = vcc icc3 vcc write status register (wrsr) current 20 40 ma program status register in progress, cs#=vcc icc4 vcc sector/block (32k, 64k) erase current (se/be/be32k) 1 40 60 ma erase in progress, cs#=vcc icc5 vcc chip erase current (ce) 1 40 60 ma erase in progress, cs#=vcc vil input low voltage -0.4 0.3vcc v vih input high voltage 0.7vcc vcc+0.4 v vol output low voltage 0.45 v iol=2ma voh output high voltage vcc-0.45 v ioh=-2ma temperature = -40 c to 85 c, vcc = 1.7v ~ 2.0v MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 77 table 15. ac characteristics symbol alt. parameter min. typ. max. unit fsclk fc clock frequency for all commands spi 133 mhz opi, dopi 200 mhz tch (1) tclh clock high time 0.45*t ns tcl (1) tcl clock low time 0.45*t ns tclch (2) / tchcl (2) clock rise time (peak to peak) / clock fall time (peak to peak) fsclk 100mhz 0.6 9 fsclk 133mhz 0.8 9 fsclk 166mhz 1 9 fsclk > 166mhz 1.2 9 tslch tcss &6fwlh6hwxs7lphuhodwlhwr6&/. 3 ns tchsl &61rwfwlhrog7lphuhodwlhwr6&/. 3 ns tshsl tcsh &6'hhohfw7lph read 10 ns write/erase/program 30 ns w'9& tdsu data in setup time str 133mhz 2 ns str > 133mhz 1 w'9& w'9&/ data setup time dtr 100mhz 1 ns dtr 133mhz 0.8 dtr 166mhz 0.6 dtr > 166mhz 0.4 tchdx tdh data in hold time str 133mhz 2 ns str > 133mhz 1 tchdx / tcldx data hold time dtr 100mhz 1 ns dtr 133mhz 0.8 dtr 166mhz 0.6 dtr > 166mhz 0.4 tchsh &6fwlhrog7lphuhodwlhwr sclk) str 3 ns tclsh &6dfwlhkrogwlph dtr 3 ns tshch &61rwfwlh6hwxs7lph (relative to sclk) str 3 ns dtr 3 ns w64= (2) tdis output disable time 5 ns w&/4/= '4suhgulhdfwlhwlph 5 ns w&/49 w&49 w9 &orfn/rwr2xwsxw9dolg loading: 30pf 8 ns loading: 20pf 7 loading: 15pf 6 loading: 10pf 5 w&/4; tho output hold time 1 ns w4649 0]'75prgh'46wr'4dolgnh&/ s) (9) 0 ns 0]'75prgh'46wr'4dolgnh&/ s) (9) 0 0]'75prgh'46wr'4dolgnh&/ s) (9) 0 0]'75prgh'46wr'4dolgnh&/ s) (9) 0 w4;46 '75prgh'4krognh loading: 30pf (9) 2.4 ns loading: 20pf (9) 2 loading: 15pf (9) 1.6 loading: 10pf (9) 1.2 temperature = -40 c to 85 MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 78 notes: 1. tch + tcl must be greater than or equal to 1/ frequency. 2. typical values given for ta=25 c. not 100% tested. 3. test condition is shown as )ljxuh and )ljxuh . 4. while programming consecutive bytes, page program instruction provides optimized timings by selecting to program the whole 256 bytes or only a few bytes between 1~256 bytes. 5. by default dummy cycle value. please refer to the 7deoh2shudwlj)uhtxhf&rpsdulr . 6. latency time required to complete erase/program suspend operation until wip bit is "0". 7. for tprs, min. timing is needed to issue next program suspend command. however, a period of time equal to/or longer than typ. timing is also required to complete the program progress. 8. for ters, min. timing is needed to issue next erase suspend command. however, a period of time equal to/or longer than typ. timing is also required to complete the erase progress. 9. dqsskw bits in cr2 must be set to the corresponding value. see "9-3-1. dq to dqs skew table" . symbol alt. parameter min. typ. max. unit tdp cs# high to deep power-down mode 10 us tres1 cs# high to standby mode without electronic signature read 30 us tres2 cs# high to standby mode with electronic signature read 30 us tw write status/confguration register cycle time 40 ms tbp byte-program 20 30 us tpp page program cycle time 0.2 1.5 ms tse sector erase cycle time 35 120 ms tbe32 block erase (32kb) cycle time 150 650 ms tbe block erase (64kb) cycle time 300 650 ms tce chip erase cycle time 200 320 s tesl erase suspend latency 25 us tpsl program suspend latency 25 us tprs latency between program resume and next suspend 0.3 100 us ters latency between erase resume and next suspend 0.3 400 us MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 79 notes : 1. sampled, not 100% tested . 2. for ac spec tchsl, tslch, tdvch, tchdx, tshsl, tchsh, tshch, tchcl, tclch in the fgure, please refer to table 15. ac characteristics. symbol parameter notes min. max. unit tvr vcc rise time 1 20 500000 us/v 13. operating conditions at device power-up and power-down ac timing illustrated in figure 109 and figure 110 are for the supply voltages and the control signals at device power-up and power-down. if the timing in the fgures is ignored, the device will not operate correctly . during power-up and power-down, cs# needs to follow the voltage applied on vcc to keep the device not to be selected. the cs# can be driven low when vcc reach vcc(min.) and wait a period of tvsl. figure 109. ac timing at device power-up sclk si cs# vcc msb in so tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl tvr vcc(min) gnd MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 80 figure 110. power-down sequence cs# sclk vcc during power-down, cs# needs to follow the voltage drop on vcc to avoid mis-operation. figure 111. power-up timing v cc v cc (min) chip selection is not allowed tvsl time device is fully accessible v cc (max) v wi MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 81 figure 112. power up/down and voltage drop table 16. power-up/down voltage and timing vcc time vcc (max.) vcc (min.) v tpwd tvsl chip select is not allowed full device access allowed pwd (max.) vwi for power-down to power-up operation, the vcc of fash device must below v pwd for at least tpwd timing. please check the table below for more detail. 13-1. initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh). the status register contains 00h (all status register bits are 0). symbol parameter min. max. unit v pwd vcc voltage needed to below v pwd for ensuring initialization will occur 0.8 v tpwd the minimum duration for ensuring initialization will occur 300 us tvsl vcc(min.) to device operation 3 ms tvr vcc rise time 20 500000 us/v vcc vcc power supply 1.7 2.0 v vwi command inhibit voltage 1.0 1.4 v MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 82 14. erase and programming performance note: 1. t ypical program and erase time assumes the following conditions: 25 c, 1.8v, and checkboard pattern. 2. under worst conditions of 85 c and 1.7v . 3. syste m-level overhead is the time required to execute the frst-bus-cycle sequence for the programming command. 4. the maximum chip programming time is evaluated under the worst conditions of 0c, vcc=1.8v, and 100k cycle with 90% confdence level. min. max. input voltage with respect to gnd on all power pins, si, cs# -1.0v 2 vccmax input voltage with respect to gnd on so -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test conditions: vcc = 3.0v, one pin at a time. parameter min. typ. max. unit write status register cycle time 40 ms sector erase cycle time (4kb) 35 120 ms block erase cycle time (32kb) 150 650 ms block erase cycle time (64kb) 300 650 ms chip erase cycle time 200 320 s byte program time (via page program command) 20 30 us page program time 0.2 1.5 ms erase/program cycle 100,000 cycles parameter condition min. max. unit data retention 55?c 20 years 15. data retention 16. latch-up characteristics MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 83 17. ordering information part no. clock (mhz) temperature package remark MX25UM51245Gxdi-05g 200 -40 c~85 c 24-ball bga (5x5 ball array) MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 84 18. part name description mx 25 um 05 xd i speed: 05: 200mhz temperature range: i: industrial (-40c to 85c) package: xd: 24-ball bga (5x5 ball array) density & mode: 51245g: 512mb type: um: 1.8v device: 25: serial flash 51245g MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information 85 19. package information MX25UM51245G rev. 0.00, nov. 24, 2014 p/n: pm2183 advanced information MX25UM51245G 86 macronix international co., ltd. reserves the right to change product and specifcations without notice. except for customized products which have been expressly identifed in the applicable agreement, macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. in the event macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said macronix's product qualifed for its actual use in accordance with the applicable laws and regulations; and macronix as well as its suppliers and/or distributors shall be released from any and all liability arisen therefrom. copyright? macronix international co., ltd.2014. all rights reserved, including the trademarks and tradename thereof, such as macronix, mxic, mxic logo, mx logo, integrated solutions provider, nbit, nbit, nbiit, macronix nbit, eliteflash, hybridnvm, hybridflash, xtrarom, phines, kh logo, be-sonos, ksmc, kingtech, mxsmio, macronix vee, macronix map, rich au dio, rich book, rich tv, and fitcam. the names and brands of third party referred thereto (if any) are for identifcation purposes only . for the contact and order information, please visit macronixs web site at: http://www.macronix.com |
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